ASNT8112-KMM

Programmable Integer Divider with SPI

Wide frequency range from DC to 32GHz
Continuous division ratios from 1 to 32
50% duty cycle of the output divided clock signal
Fully differential CML input and output interfaces
Adjustable Power Consumption
Easy 5-bit parallel programming interface compatible with CMOS/LVTTL standards
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Frequency (min): DC
Frequency (max): 32 GHz
Power: 1400 - 2240 mW
Package: 44-pin CQFP
Price: Request

Product Details

Fig. 1 Functional Block Diagram

ASNT8112-KMM is a high-speed programmable integer clock divider with dynamic adjustment of the division ratio. The divider accepts an input clock signal (chip/chin) with a speed from DC to the maximum specified frequency, and provides a clean 50% duty cycle output divided clock signal (cop/con) in any operational mode. The divider allows for dynamic adjustment of the division ratio from 1 to 32 with a step of 1 through either a full-scale CMOS 5-bit parallel interface, or a 1.2V CMOS 3-wire SPI. The parallel or serial interface mode is selected via the SPI interface. If the SPI interface is not connected, the parallel controls are active by default.

In parallel mode, a binary code on the control inputs (c0-c4) defines the value of the ratio from 1 to 32, where c4 is the most significant bit (MSB). All “0”s (“low” state) defines division by 32. Following the change of any control signal, the divider switches to idle after (64…128) periods of the high-speed system clock plus an additional 1.6ns delay, and returns back to normal operation with the new division ratio after an additional delay equal to 192 periods of the high-speed system clock.

In serial mode, the 1-byte division coefficient code is supplied through the 3-wire interface with MSB first. The input data 3wdin is sampled at rising edges of the SPI clock 3wcin, and the internal division coefficient value will be updated at the rising edge of the 3wenin signal. The first two bits are not functional, and the third bit SO enables the serial interface (SPI ON) which then allows bits C4 through C0 to set the division ratio. The device automatically resets itself after initial power-up, and any change of the division control signals.

The part’s I/O’s support the CML logic interface with on chip 50Ω termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination. In the DC-coupling mode, the input signal’s common mode voltage should comply with the specifications shown in the electrical characteristics section within the part’s datasheet. In the AC-couping mode, the input termination provides the required common mode voltage automatically. The differential DC signaling mode is recommended for optimal performance.