ASNT2111-KMF

1:2 Reconfigurable Demultiplexer with Integrated Half Rate PAM4 CR

1:2 demultiplexer (DMUX) with integrated full-rate CDR
Input Data range from 18GHz to 36GHz
NRZ Input Data Format
CML compliant differential input and output high-speed data and clock interfaces
1.3V CMOS 3-wire Interface for digital controlsw
LVDS or CML compliant input reference clock interface
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Frequency (min): 18 GHz
Frequency (max): 36 GHz
Power: 1800 mW
Package: 64-pin CQFP
Price: Request

Product Details

Fig. 1. Functional Block Diagram

ASNT2111-KMF is a 1:2 demultiplexer (DMUX) with full-rate integrated clock and data recovery (CDR). The IC shown in Fig. 1 functions in CDR mode covering a wide range of input data rates (fbit) by utilizing its six on-chip VCOs (voltage-controlled oscillators). To reduce the physical number of control inputs to the chip, a shift register with a 3-wire input interface (SPI) has been included on chip. The SPI block provides all the digital controls for the chip. It also provides digital controls for digital-to-analog converters (DACs) that handle internal analog DC voltage adjustments.

 

Selection of the desired working data rate of the CDR is accomplished through the digital control vcosel (see Table 1). An external low speed system clock c32p/c32n running at 1/32 the frequency of the active VCO must be applied to the low-speed clock input buffer (CLK IB).

 

The main function of the chip is to convert a RZ or NRZ input data signal dp/dn with a bit rate of fbit accepted by CML buffer (Data IB) into 2 parallel NRZ data signals q0p/q0n and q1p/q1n running at bit rates of fbit/2 and delivered to the outputs by CML data output buffers (D2OBx2). The clock and data are recovered from the input data stream by the CDR.

 

A full rate retimed NRZ data output signal dop/don is also available through the CML data output buffer (DOB) allowing the part to be used as a 1:1 CDR. Half rate clock c2p/c2n delivered through the CML clock output buffer (COB) has a tight phase alignment to the demultiplexed data output signals q0p/q0n and q1p/q1n.

 

Data IB can operate with either differential or single-ended input signals. It includes tuning pins dcinp/dcinn for DC offset of the input signals in case of AC termination. When the buffer is operating with a DC-terminated single ended input signal, a correct threshold voltage should be applied to the unused input pin. A peak detector is also included to provide means of demodulating AM components carried by the input data with frequency ranges of up to a few hundred kHz. The peak detector’s output signal is delivered to the differential port pkdtp/pkdtn. All CML I/Os provide on chip 50Ohm termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLY CONFIGURATION). Output buffers DOB, COB, and D2OBx2 can be individually disabled through control bits ondo, onco, and ond2o to save power.