ASNT8730-KHC

High-Speed Clock Divider-by-2

High-speed broadband clock divider by 2
Exhibits low jitter and limited temperature variation over industrial temperature range
Fully differential CML input interface
Fully differential CML output interface with 400mV single-ended swing
Single +3.3V or -3.3V power supply
Power consumption: 460 mW
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Frequency (min): DC
Frequency (max): 64 GHz
Power: 460 mW
Package: 24-pin CQFN
Price: Request

Product Details

Fig.1 Functional Block Diagram

The ASNT8730-KHC provides broadband clock divide-by-2 functionality, and is intended for use in high-speed measurement / test equipment. The IC can process a high-speed clock input signal cp/cn and deliver a high-speed clock output signal qp/qn with 50% duty cycle. Static control signals iboff and iefoff provide option to increase device bandwidth by slightly increasing power consumption. In default (unconnected) state control signals are pulled-up to vcc to save power consumption. To activate boost mode low level voltage should be provided to both or just one of control inputs.

The part’s I/O’s support the CML logic interface with on chip 50 Ohms termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination. In the AC-coupling mode, the input termination provides the required common mode voltage automatically. The differential DC signaling mode is recommended for optimal performance.