ASNT6119-KMF (Pre-Emphasis Amplifier)

Advanced Driver / Amplifier with Digital Pre-Emphasis, PAM4 Encoding, less than 200fs p-p Jitter, and standard CMOS 3-wire SPI Interface

High-speed limiting amplifier with selectable built-in pre-emphasis
Four pre-emphasis taps with externally controlled weight and inversion
Adjustable data output amplitude and eye quality
Single-ended output data eye cross point adjustment
Optional main clock frequency multiplier by 2
Main clock duty cycle indicators located before and after the multiplier
Show all features
Package Footprint Data Sheet Software Request Quote
Frequency (min): 1.0 Gbps
Frequency (max): 32.5 Gbps
Power: 4000 mW
Package: 64-pin CQFP
Price: Request

Product Details

asnt6119-kmf desc

Fig.1 Functional Block Diagram

The ASNT6119-KMF is a Pre-Emphasis Amplifier, Pre-Emphasis Driver, and PAM4 Test Signal Generator. With its usage as a Pre-emphasis Amplifier, the amplitudes of modulating voltage can be boosted in order to generate louder frequencies. The ASNT6119-KMF SiGe component shown in Fig. 1 generates a combination of four delayed copies of its input differential data signal dp/dn with certain user-controlled weights and polarities. The copies are generated in a 4-bit shift register controlled by the internal high-speed clock signal. This clock signal is derived from the main input clock ci0p/ci0n with either matching or doubled frequency. The duty cycles of the input and internal clock signals are monitored during multiplication, and the output duty cycle can be adjusted through the external control port phadj. For optimal performance, the input data rate in Gbps should be equal to the internal clock frequency in GHz.

Input clock and data signals can be delayed in the same or opposite directions to provide the optimal phase relation at the inputs of the shift register and at the chip outputs. The component can also provide clock buffering for an additional clock signal ci1p/ci1n. This signal can then be delivered to the output port cop/con instead of the main clock ci0p/ci0n.Amplitude and peaking of the clock and data output signals can be adjusted externally. Both single-ended data output signals also have controlled DC common-mode levels and eye crossing points. All operational modes of the chip are controlled through a SPI running on ADSANTEC’s proprietary software.

The part’s I/Os support the CML logic interface with on chip 50Ω termination to Ground and may be used differentially, AC/DC coupled, single-ended, or in any combination. In the DC-coupling mode, the input signal should have a specific common mode voltage. In the AC-coupling mode, the input termination provides the required common mode voltage automatically. Optimal performance is achieved with differential DC signaling mode.

The chip operates from one negative power supply (positive pin connected to external Ground, negative pin vee = -4.3V) and one floating positive power supply (negative pin connected to vee and positive pin v3p5 = 3.5V). It is recommended to keep the relative deviation of v3p5 from Ground within less than ±0.1V.