Delay Line: Ensure Critical System Timing Points are met using a Signal Delay Line
A signal delay line is a product that takes an input signal (in this case a clock or data signal using high speed CML) and outputs it at a fixed delay that is slightly adjustable. Adjustment can be either through digital or analog means where the allowed maximum frequency of adjustment can be important in some cases.
Both passive and active solutions exist for frequencies above 1.0GHz/1.0Gbps. Passive delay lines tend to be narrow band (i.e. they only work for specific frequencies of clock and don’t work for data) and support a large form factor. They also introduce loss to the signal, which is unwanted at any frequency of operation, especially at high frequencies. An active phase shifter provides gain, restores the input signal if needed, and is much smaller in size, which is beneficial in highly integrated, compact systems. The rate of delay change can be much higher in active delay lines too (>1.0GHz) and much finer (<1.0ps of resolution).
ADSANTEC’s product ASNT5105A-KMC is a DC to 50Gbps/32GHz active delay line. While the part has an inherent fixed delay, it can be increased up to 110ps more (at a 1.0GHz rate) with femtosecond precision using included externally electrical controlled knobs. Input signals can be as low as 50mVpk-pk (single-ended or differential) and the part will still produce output signals limited to the amplitude of 450mVpk-pk single-ended (900mVpk-pk differential).
The two differential signal I/Os and the delay tuning port utilize 50ohm impedance networks since they feature the CML family. All three ports can function with either differential or single-ended signaling.
Common application areas include test and measurement equipment and R&D bench top setups. Delay lines are more valuable in higher frequency systems where even precise PCB layouts are not good enough to ensure all critical timing points are met over a broad frequency range with mismatched components. The inclusion of the phase shifters afford the system designer flexibility if he/she wishes to makes changes in the future without having to go through a complete redesign.